Photovoltaic cell with porous semiconductor regions for anchoring contact terminals, electrolitic and etching modules, and related production line

ABSTRACT

A photovoltaic cell ( 100 ) is proposed. The photovoltaic cell includes a substrate ( 105; 105 ′) of semiconductor material, and a plurality of contact terminals (Tf,Tb) each one arranged on a corresponding contact area ( 122 ) of the substrate for collecting electric charges being generated in the substrate by the light. For at least one of the contact areas, the substrate includes at least one porous semiconductor region ( 125 ) extending from the contact area into the substrate for anchoring the whole corresponding contact terminal on the substrate. In the solution according to an embodiment of the invention, each porous semiconductor region has a porosity decreasing moving away from the contact area inwards the substrate. An etching module ( 400 ) and an electrolytic module ( 700;700′;800;800 ′) for processing photovoltaic cells, a production line ( 900 ) for producing photovoltaic cells, and a process for producing photovoltaic cells are also proposed.

TECHNICAL FIELD

One or more embodiments relate to the field of photovoltaicapplications. More specifically, one or more embodiments relate tophotovoltaic cells. Moreover, further embodiments relate to the field ofelectrolytic processes and to the field of etching processes. Morespecifically, these embodiments relate to electrolytic modules (forexample, for performing anodization processes and deposition processes)and to etching modules—for example, for use in production lines ofphotovoltaic cells.

BACKGROUND

Photovoltaic cells are commonly used to convert light energy intoelectric energy (being also known as solar cells for use with the sunlight). The most common type of solar cell is based on a semiconductorsubstrate (for example, made of silicon), wherein a PN junction isformed between a front surface and a back surface thereof; the sun lightthat is absorbed by the front surface of the substrate generateselectric charges (i.e., electron-hole pairs), which supply acorresponding current to an external load.

Each solar cell generally has a front contact terminal on the frontsurface and a back contact terminal on the back surface for its couplingto the external load. The back contact terminal may extend throughoutthe whole back surface (since it is usually not reached by the sunlight), so that it may be relatively thin. Conversely, the front contactterminal is typically maintained as small as possible, in order to limitthe obscuring of the front surface to the sun light (for example, in theform of a grid with narrow contact strips); therefore, the front contactterminal is typically relatively thick (to reduce its resistance alongthe contact strips on the front surface).

A problem of each solar cell known in the art is the difficulty ofmaintaining the contact terminals fixed on the substrate, especially forthe front contact terminal because of its small size and high thickness.Indeed, even a slight loss of adhesion of each contact terminal involvesa non-uniformity or instability of its contact resistance, therebycausing a current concentration on the rest of the contact terminal; asa result, the contact terminal heats up with its progressive loss ofadhesion. All of the above has a detrimental effect on the efficiency ofthe solar cell.

For this purpose, several techniques have been proposed to improve theadhesion of the front contact terminal (and of the back contact terminalas well) on the substrate.

For example, a known technique is based on applying a metal paste (forexample, by a screen-printing process), and then performing a firingprocess (so as to anchor the metal paste on the substrate). However, thefiring process requires the application of very high temperatures (ofthe order of 400-750° C.), which induce mechanical stresses on the solarcell (because of the different thermal expansion coefficients of itsmaterials). Therefore, the solar cell is maintained relatively thick(for example, with a thickness of at least 150-200 mm), in order tosustain these mechanical stresses without cracking. The application ofthe metal paste also involves high production costs. Moreover, the metalpaste provides a relatively high resistance of the contact terminals(which adversely affect the efficiency of the solar cell).

Another known technique is instead based on forming grooves on the frontsurface of the substrate (for example, by a laser ablation process), andthen depositing a metal layer into them; these groves are relativelydeep (for example, 3-60 μm), so that the front contact terminal soobtained is buried (at least partially) into the substrate (therebyremaining mechanically anchored to it). However, the groves weaken themechanical structure of the solar cell. Therefore, as above the solarcell is maintained relatively thick (in order to avoid its cracking).

Porous silicon is also used in the production of the solar cells to forman antireflection coating (ARC) on the font surface of the substrate.

For example, Vinod et al., “The ohmic properties and current-voltagecharacteristics of the screen-printed silicon solar cells with poroussilicon surface”, Solid State Communications, Pergamon, GBLNKD—DOI:10.1016/J.SSC.2009.02.019, vol.149, no.23-24, pages 957-961,XP026098082 ISSN: 0038-1098 (the entire disclosure of which is hereinincorporated by reference) indicates that the solar cells may beproduced forming the contact terminals by a screen printing step of anAg paste followed by its firing (at 725° C.); the porous silicon is thenformed by electrochemical etching on the n⁺-Si surface (in most caseswithout any protective cover of the Ag contacts). Alternatively (inorder to avoid corresponding problems), the same document also indicatesthat the porous silicon may be formed first followed by the formation ofthe Ag contacts thereon; a firing step at 700-825° C. following by anannealing step at 450° C. are then performed to facilitate the formationof an ohmic contact between Ag and n⁺-Si (by driving molten glass fritcontained in the Ag contacts nearly completely to pierce through theentire thickness of the porous silicon layer, thereby creatingspike-like direct Ag—Si interconnections). The document Vinod et al.explicitly indicates that the firing step has to be performed at veryhigh temperature (because “low temperature firing at 700° C. is notsufficient to wet and to etch completely the entire thickness of theporous silicon film”). Upon cooling, the Ag/Si layer recrystalizes so asto create the desired ohmic contact.

The step of forming the porous silicon is performed with constantprocess parameters (i.e., current density). Moreover, therecrystalization process (especially of an alloy like the Ag/Si layer)normally generates a homogeneous structure (for example, see B.Arzamasov, Material Science Edit, Mir Publisher Moscow, Englishtranslation 1989, chapter 4.3, page 91, ISBN 5-03-000074-7, the entiredisclosure of which is herein incorporated by reference, wherein thereis stated that “recrystallization is understood as the nucleation andgrowth of new grains with a smaller number of structural defect [sic];recrystallization results in the formation of entirely new, most oftenequiaxed crystals” and that “as a rule, recrystallized alloy [sic] arehomogeneous in their properties and exhibit no anisotropy”). Moreover,the high temperature to which the porous silicon is subject after itsformation tends to reduce the superficial porosity (for example, see M.Banerjee et al., “Thermal annealing of porous silicon to develop a quasimonocrystalline structure”, J Mater Sci: Mater Electron (2009)20:305-311 DOI 10.1007/s10854-008-9725-y, the entire disclosure of whichis herein incorporated by reference, wherein there is stated that aftera thermal treatment “porous silicon was transformed into quasimonocrystalline porous silicon with a smooth surface and with few voidsembedded inside the body”).

Moreover, US-A-2009/0188553 (the entire disclosure of which is hereinincorporated by reference) proposes using a porous silicon layer on thefront surface to prevent recombination of the generated electriccharges. Alternatively, the porous silicon layer may be used to getterimpurities of the substrate; in this case, the substrate is annealed todiffuse the impurities into the porous silicon layer, which is thenremoved. The same document also suggests plating the front contactterminal on an adhesion-promoting porous silicon layer. For thispurpose, grooves are made on the front surface; the porous silicon layeris then formed within the grooves, so as to provide anadhesion-promoting surface for the next plating of corresponding buriedelectrical contacts (with another porous silicon layer that may also beformed on the back surface, for its passivation followed by the openingof windows for contacting the substrate by a metallization layer that isdeposited over this passivation layer). In another embodiment, ametallization layer is directly deposited on a porous silicon layer thatis formed on the whole back surface; in this case, the front contactterminals are plated on corresponding electrical contact regions, whichare obtained by selectively irradiating a photo-catalyst layer on whicha hole-scavenger layer is applied. At the end, in a different embodimentthe front contact terminals are formed by plating correspondingprecursor electrical contacts; the precursor electrical contacts areformed on a porous silicon layer by a screen-printing and etchingprocess. However, these techniques suffer from the same drawbackspointed out above—i.e., the weakening of the mechanical structure beingcaused by the grooves (that requires the solar cell to be maintainedrelatively thick), and the high production costs being caused by theformation of the electrical contact regions or the precursor electricalcontacts.

The porous silicon is also used in completely different applications.For example, in WO/2007/104799A1 (the entire disclosure of which isherein incorporated by reference) a porous silicon layer is formed on asubstrate to facilitate the raising of leads being formed thereon, so asto obtain corresponding interconnection elements (after the substratehas been removed). For this purpose, the porous silicon layer isconfigured to allow the peeling of a portion of the leads from thesubstrate, but at the same time preventing their complete detachment;particularly, the porous silicon layer has a porosity that preferablydecreases moving towards its portion to be raised. In any case, theporous silicon layer is relatively thick (for example, at least 2 μm),with a porosity that may also decrease moving inwards the substrate(with the resulting weakening of the substrate that it is not a problem,since it is generally removed after the formation of the raised leads).

In general terms, one or more embodiments are based on the idea of usingthe porous silicon to anchor the contact terminals on the substrate ofthe solar cells (or more generally, of the photovoltaic cells).Moreover, one or more embodiments are based on the idea of using adynamic meniscus for implementing an electrolytic module or an etchingmodule (which electrolytic module and/or etching module may also be usedto implement a production line of the photovoltaic cells).

More specifically, an embodiment provides a photovoltaic cell (or solarcell) including a substrate of semiconductor material (for example,silicon). The photovoltaic cell includes a plurality of contactterminals; each contact terminal is arranged on a corresponding contactarea of the substrate for collecting electric charges that are generatedin the substrate by the light (for example, on a front surface and/or ona back surface of the substrate). For one or more of the contact areasthe substrate includes at least one porous semiconductor region (forexample, porous silicon), which extends from the contact area into thesubstrate for anchoring the whole corresponding contact terminal on thesubstrate. In an embodiment, each porous semiconductor region has aporosity decreasing moving away from the contact area inwards thesubstrate.

Another embodiment provides an etching module for performing an etchingprocess on a substrate (for example, for processing these photovoltaiccells). The etching module includes an etching head. In turn, theetching head includes a support element having an operative surface. Theetching head then includes one or more delivery mouths for delivering anetching solution on the operative surface. The etching head furtherincludes one or more suction mouths (completely surrounding the deliverymouths on the operative surface) for sucking the delivered etchingsolution; in this way, there is formed a dynamic meniscus on theoperative surface when in contact with a corresponding portion of thesubstrate.

Another embodiment provides an electrolytic module for performing anelectrolytic process (for example, an anodization process or adeposition process) on a substrate (for example, for processing thesephotovoltaic cells). The electrolytic module includes a set ofprocessing heads. In turn, each processing head includes a supportelement having an operative surface. The processing head then includesone or more delivery mouths for delivering a solution on the operativesurface (with the support element that is made at least partially of anelectrically conductive material for contacting the solution). Theprocessing head further includes one or more suction mouths (arrangedaround the delivery mouths on the operative surface) for sucking thedelivered solution; in this way, there is formed a dynamic meniscus onthe operative surface when in contact with a corresponding portion ofthe substrate. One of the processing heads is an electrolytic head forproviding a dynamic meniscus of an electrolytic solution. Theelectrolytic module further includes first biasing means for applying afirst biasing voltage to the electrolytic solution through theelectrolytic head, and second biasing means for applying a secondbiasing voltage to the substrate.

A further embodiment provides a production line for producing thesephotovoltaic cells. The production line includes an etching station; inturn, the etching station includes a set of etching modules as above,each one for clearing a corresponding portion of a contact area on eachsubstrate currently in the etching station. In addition or inalternative, the production line also includes an anodization station;in turn, the anodization station includes a set of electrolytic modulesas above, each one for forming a corresponding portion of a poroussemiconductor region in the contact area of each substrate currently inthe anodization station. In addition or in alternative, the productionline further includes a deposition station; in turn, the depositionstation includes a set of further electrolytic modules as above, eachone for forming a corresponding portion of a contact terminal on thecontact area of each substrate currently in the deposition station.

A different embodiment provides a process for producing a photovoltaiccell. Particularly, the process includes the step of providing asubstrate of semiconductor material, which has a front surface forabsorbing the light. At least one front contact terminal is then formed;the contact terminal is arranged on a front contact area of the frontsurface for collecting electric charges being generated in the substrateby the light. In an embodiment, the front contact area and the frontcontact terminal have a flat profile. The step of forming at least onefront contact terminal includes forming at least one front poroussemiconductor region, which extends from the front contact area into thesubstrate for anchoring the whole front contact terminal on thesubstrate. The process further includes chemically depositing the frontcontact terminal

In an embodiment, the same steps may also be executed to form at leastone back contact terminal on a back surface of the substrate (oppositeits front surface).

BRIEF DESCRIPTION OF THE DRAWINGS

One or more embodiments, as well as features and the advantages thereof,will be best understood with reference to the following detaileddescription, given purely by way of a non-restrictive indication, to beread in conjunction with the accompanying drawings (whereincorresponding elements are denoted with equal or similar references andtheir explanation is not repeated for the sake of brevity). In thisrespect, it is expressly intended that the figures are not necessarydrawn to scale (with some details that may be exaggerated and/orsimplified) and that, unless otherwise indicated, they are merely usedto conceptually illustrate the structures and procedures describedherein. Particularly:

FIG. 1 shows a simplified cross-section view of a solar cell accordingto an embodiment,

FIG. 2A-2H show the main stages of a process for producing a solar cellaccording to an embodiment,

FIG. 3A shows a scanning electron microscopy photo of a porous siliconregion according to an embodiment,

FIG. 3B shows a schematic cross-section view of a porous silicon regionaccording to another embodiment,

FIG. 4A-FIG. 4B show a simplified cross-section view and bottom view,respectively, of a processing head that may be used to process the solarcell according to an embodiment.

FIG. 5A-5B show the main stages of a process for producing thisprocessing head according to an embodiment,

FIG. 6A-6B show an exemplary etching module that may be used to processthe solar cell according to an embodiment in different operativeconditions,

FIG. 7A-7C show two exemplary anodization modules that may be used toprocess the solar cell according to corresponding embodiments indifferent operative conditions,

FIG. 8A-8C show two exemplary deposition modules that may be used toprocess the solar cell according to corresponding embodiments indifferent operative conditions,

FIG. 9A shows a schematic block diagram of a production line of solarcells according to an embodiment, and

FIG. 9B-FIG. 9Q show different exemplary architectures of thisproduction line according to corresponding embodiments in differentoperative conditions.

DETAILED DESCRIPTION

With reference now to FIG. 1A, there is shown a simplified cross-sectionview of a solar cell 100 according to an embodiment.

Particularly, the solar cell 100 is made in a silicon substrate 105 (forexample, with a size of 156 mm×156mm) The substrate 105 has a front(upper) surface, which will be exposed to the sun light during operationof the solar cell 100, and a back (lower) surface opposite thereto. Thesubstrate 105 includes an upper N-type layer 115 and a lower P-typelayer 120, which form a (metallurgic) PN junction (with the frontsurface and the back surface of the substrate 105 that are defined by anexposed surface of the N-type layer 115 and by an exposed surface of theP-type layer 120, respectively).

A front contact terminal Tf (or more) and a back more contact terminalTb (or more) are formed on the front surface and on the back surface,respectively, of the substrate 105 for collecting electric charges beinggenerated in the substrate 105 by the sun light. Typically, the frontcontact terminal Tf extends on a small contact area 122 of the frontsurface of the substrate 105, which is exposed by a correspondingcontact window being opened through a protective layer 123 of thesubstrate 105 (so as to limit the obscuring of its front surface to thesun light); for example, the front contact terminal Tf has a gridstructure, with a plurality of narrow contact strips (extendingthroughout the whole solar cell—e.g., with a width of approximately5-200 μm) that are coupled to a pair of larger contact strips, or buses(e.g., with a width of approximately 0.5-3 mm) Therefore, the frontcontact terminal Tf is relatively thick (for example, with a thicknessof approximately 10-50 μm), in order to reduce the correspondingresistance (along the length of its contact strips and contact buses onthe front surface of the substrate 105). On the contrary, the backcontact terminal Tb typically extends throughout the whole back surfaceof the substrate 105 (in such case being not reached by the sun light inany case), without any constraint on its size and thickness.

In an embodiment, as described in detail in the following, a poroussilicon region 125 (or more) extends from the contact area 122 in thesubstrate 105 (under the front contact terminal Tf).

The porous silicon region 125 strongly enhances an adhesion of the wholefront contact terminal Tf on the contact area 122; therefore, the frontcontact terminal Tf is firmly anchored on the substrate 105, therebywarranting a stable contact resistance.

Moreover, it has been discovered, with great surprise, that in this waythe front contact terminal Tf remains anchored on the front surface ofthe substrate 105 even if both of them are flat, irrespectively of thesize and/or thickness of the front contact terminal Tf. As usedhereinafter, the term flat means that the front surface of the substrate105 does not have any groove for increasing the adhesion as in the priorart (with a width and/or a depth of the same order of magnitude as thesize of the front contact terminal Tf—i.e., its width and height,respectively). Naturally, this does not exclude the possibility ofhaving very small irregularities on the front surface of the substrate105 (i.e., with a width and/or a depth at least one or two orders ofmagnitude lower than the size of the front contact terminal Tf); forexample, this typically happens when the front surface of the substrate105 is textured to reduce its reflection at the dominant wavelength ofthe sun light (for example, by an anisotropic etching process).

All of the above allows working a very thin substrate 105 for making thesolar cell 100 (for example, with a thickness of approximately 20-100nm), with a beneficial effect on its cost.

At the same time, the porous silicon region 125 also acts as a getteringcenter for impurities of the substrate 105 (for example, metals andoxygen); this increases the lifetime of the electrons and holes in thesubstrate 105. Therefore, the above-described embodiment has abeneficial effect on the lifetime of the light generated electriccharges (i.e., electrons and holes) of the solar cell 100.

In addition or in alternative, a porous silicon region 130 (or more) maylikewise extend from the back surface in the substrate 105 under theback contact terminal Tb. As above, the porous silicon region 130strongly enhances an adhesion of the whole back contact terminal Tb, sothat the back contact terminal Tb as well is firmly anchored on thesubstrate 105 (in addition to act as a gettering center for theimpurities of the substrate 105).

In both cases, the increased adhesion being provided by the poroussilicon regions 125, 130 allow making the front and/or back contactterminals Tf, Tb by means of a chemical (or wet) deposition process,with little or no risk of their detachment from the substrate 105 (so asto warrant a stable contact resistance). As a result, it is possible toreduce the temperatures to which the solar cell 100 is subject duringits production process (for example, working at room temperature, or inany case below approximately 300-350° C.), so as to avoid, or at leaststrongly reduce, any mechanical stresses on the solar cell 100 (beingdue to the different thermal expansion coefficients of its materials).This further reduces the production cost of the solar cell 100, andsignificantly reduces the resistance of the contact terminals Tf, Tbwith a corresponding improvement of the efficiency of the solar cell100.

With reference now to FIG. 2A-2H, there are shown the main stages of aprocess for producing this solar cell according to an embodiment.

As shown in the example of FIG. 2A, the production process starts with asilicon wafer (of mono-crystalline or poly-crystalline type) thatdefines the substrate 105 of the solar cell; the wafer 105 is of theP-type of conductivity (for example, with a resistivity of approximately1-3 Ω·cm). Optionally, a highly doped P-type contact layer (not shown inthe figure) may also be formed extending from the back surface in thewafer 105 (in order to provide a good ohmic contact with thecorresponding back contact terminal). The porous silicon region 130 ismade extending from the back surface into the wafer 105—for example,throughout its whole extent with a depth of approximately 0.05-1 μm(such as approximately 0.3 μm). For this purpose, the wafer 105 issubject to an anodic process (described in detail in the following),wherein the wafer 105 is used as an anode in an electrolytic cell (at apositive voltage with respect to a negative voltage of a cathodethereof).

The production process continues to FIG. 2B, wherein the N-type layer115 is made extending from the front surface into the wafer 105 (forexample, by a diffusion or implantation process); in this way, aremaining portion of the wafer 105 defines the P-type layer 120 (whichforms the desired PN junction with the N-type layer 115, being buried inthe wafer 105 proximate to its front surface). For example, the N-typelayer 115 has a depth of approximately 0.2-1.5 μm (such as approximately0.3-0.7 μm). The doping concentration of the N-type layer 115 has aGaussian profile, which decreases from a peak at the front surface ofthe wafer 105 until reaching the same value of the P-type layer 120 attheir interface. For example, the peak doping concentration of theN-type layer 115 is of approximately 5.10¹⁹-2.10²⁰ atoms/cm³. Otherwise,when the doping concentration of the N-type layer 115 is lower thanapproximately 1.10¹⁹ atoms/cm³, one or more highly doped N-type contactregions (not shown in the figure) may be formed extending from the frontsurface into the wafer 105 (in correspondence to the front contactterminal, in order to provide a good ohmic contact therewith); forexample, these N-type contact regions have a depth of approximately 2-3μm, and a peak doping concentration (starting from the front surface ofthe wafer 105) of approximately 1.10²⁰-1.10²¹ atoms/cm³.

With reference to FIG. 2C, during the diffusion process of the N-typelayer 115 a thin oxide layer 205 and a thin oxide layer 210 form on thefront surface and on the back surface, respectively, of the wafer 105.An anti-reflection coating 215 is then applied on the oxide layer 205(with the oxide layer 210 and the anti-reflection coating 215 that formthe protective layer 123 of the front surface of the wafer 105); forexample, the anti-reflection coating 215 is made of silicon nitride(Si₃N₄), which is usually deposited by a plasma enhanced chemical vapourdeposition (PECVD) process. The oxide layer 210 on the back surface ofthe wafer 105 is then removed—for example, by immersing the wafer 105into a buffered Hydrofluoric (HF) acid solution.

Proceeding to FIG. 2D, a thin metal layer 220 is made on the backsurface of the wafer 105 (i.e., on the porous silicon region 130) by anelectro-less deposition process;

for example, the thin metal layer 220 is made of Nichel (Ni), with athickness of 0.1-2 μm.

As shown in FIG. 2E, the contact window for the front contact terminalis opened in the protective layer 123 (i.e., the oxide layer 205 and theanti-reflection coating 215); for example, this contact window is madeby a standard photo-lithographic process (wherein a photo-resist layeris patterned photo-lithographically to obtain a correspondingphoto-resist mask, with the anti-reflection coating 215 and the oxidelayer 205 being not protected by the photo-resist mask that are thenetched—for example, through a dry or wet etching process). The contactwindow exposes the corresponding contact area 122 of the front surfaceof the wafer 105, with the possible N-type contact region (not shown inthe figure).

In the contact area 122, the porous silicon region 125 is then madeextending from the front surface into the wafer 105—for example, with adepth of approximately 0.05-1 μm (such as approximately 0.2 μm). Forthis purpose, the wafer 105 is again subject to an anodic process(described in detail in the following), wherein the wafer 105 is used asan anode (at a positive voltage) in an electrolytic cell (with anelectrolytic solution that does not damage the anti-reflection coating215 or with a photo-resist mask, not shown in the figure, which protectsthe anti-reflection coating 215); in this respect, it is noted that thepositive voltage that is applied to the back surface of the wafer 105forward biases the PN junction 120-115, so that is does not interferewith the anodic process.

Moving to FIG. 2F, a thin metal layer 225 is made on the front surfaceof the wafer 105 (i.e., on the porous silicon region 125 and on theanti-reflection coating 215, after removing its possible protectionmask) by an electro-less deposition process; for example, as above thethin metal layer 225 is made of Nickel, with a thickness ofapproximately 0.1-1 μm. Optionally, the wafer 105 may now be subject toa rapid thermal annealing process to form a Nickel Silicide (Ni₂Si)layer at the interface between the porous silicon layer 130 and the thinmetal layer 220, and at the interface between the porous silicon region125 and the thin metal layer 225 (in order to reduce a correspondingcontact resistance); this annealing process is performed at relativelylow temperature, usually below approximately 350° C., and for a shortperiod (for example, at approximately 200° C. for approximately 60 s).

The production process continues to FIG. 2G, wherein a photo-resist mask230 is made on the thin metal layer 225, so as to leave exposed it incorrespondence to the contact window on the front surface of the wafer105 (for example, by a standard photo-lithographic process). A thickmetal track 235 is made on the thin metal layer 225 being exposed by thephoto-resist mask 230 (i.e., on the contact window), and a thick metallayer 240 is made on the thin metal layer 220 by an electrolyticdeposition process (with the required biasing voltage that is applied tothe wafer 150 through the thin metal layers 220 and 225); for example,the thick metal track 235 and the thick metal layer 240 are made ofCopper (Cu), with a thickness of approximately 5-50 μm. The photo-resistmask 230 is then stripped.

With reference now to FIG. 2H, the front surface of the wafer 105 issubject to a dry or wet etching process, until the thin metal layer 225being not protected by the thick metal track 235 is removed, therebyexposing the anti-reflection coating 215 (for example, by a dry or wetetching process wherein the thick metal track 235 acts as a mask). Inthis way, there is obtained the desired solar cell 100. Particularly,the remaining portion of the thin metal layer 225 and the thick metaltrack 235 on top of it define the front contact terminal Tf; likewise,the thin metal layer 220 and the thick metal layer 240 on top of itdefine the back contact terminal Tb.

The above-described electrolytic deposition process allows obtainingvery thick front and back contact terminals Tf, Tb in a relatively shorttime (with a consequent reduction of the production cost of the solarcell 100). In this respect, it should be noted that in a conventionalelectrolytic cell (being used to perform the above-mentionedelectrolytic deposition processes) the wafer 105 is used as a cathode.Therefore, the corresponding negative voltage being required to bias thewafer 105 cannot be applied to its back surface to form the thick metaltrack 235 of the front contact terminal Tf (since the PN junction120-115 would be reverse biased thereby acting as a blocking contact);for this reason, the thin metal layer 225 is previously made on thefront surface of the wafer 105 by an electro-less deposition process, soas to allow applying the required negative voltage thereto.

Moving now to FIG.3A-FIG.3B, different techniques may be used to makeeach porous silicon region (either on the front surface or on the backsurface of the wafer). For example, in an embodiment the porous siliconregion is obtained by an anodic process (wherein the wafer is used as ananode in an electrolytic cell including an electrolytic solution beingrich of HF acid). When a current density of the anodic process is lowerthan a critical value J_(PS) (depending on multiple experimentalfactors), the electrolytic solution only reacts with holes that reachthe exposed surface of the wafer (so that the reaction is limited by thefeeding of the holes and not by their ionic diffusion into theelectrolytic solution). Of course, this requires the availability of(free) holes at the exposed surface of the wafer. When the poroussilicon region is made on the back surface of the wafer, the holes areobviously available in the corresponding P-type layer. Conversely, whenthe porous silicon region is made on the front surface of the wafer, theinterface between the corresponding N-type layer and the electrolyticsolution acts as a reverse-biased Schottkly junction (i.e., with adepletion region whose width decreases as the concentration ofimpurities in the N-type layer increases). Therefore, when the N-typelayer has a high concentration of impurities (i.e., at leastapproximately 1.10¹⁷ atoms/cm³), the free holes in the N-type layer canpass through the potential barrier of this junction byquantum-mechanical tunneling; conversely, it is necessary to provideenergy to the holes for allowing their passage through the potentialbarrier—for example, by lighting the wafer on its front and/or backsurface. This means that if the anodic process is performed in a darkcondition (for example, below approximately 0.2-2 lux, such as belowapproximately 1 lux), the porous silicon region can only be obtained inthe external portion of the N-type layer having a doping concentrationat least equal to approximately 1.10¹⁷ atoms/cm³. Therefore, the dopingconcentration profile of the N-type layer may be used to control thedepth of the porous silicon region in a very simple and accurate way;for this purpose, it is enough to provide the external portion of theN-type layer with this doping concentration for the desired thickness ofthe porous silicon region, and a remaining portion of the N-type layerwith a lower doping concentration (so that the anodic process will stopautomatically after the conversion of the whole external portion of theN-type layer into porous silicon). In any case (i.e., when a lower depthis desired, when the N-type layer has a higher doping concentration, orwhen the wafer is illuminated) the depth of the porous silicon regioncan be controlled by varying the length of the anodic process.

The porous silicon so obtained has a complex structure with a randomnetwork of small pores. The characteristics of the porous silicon dependon its morphology, which in turn is a function of a regime of the anodicprocess being defined by different parameters (for example, the length,the concentration and the type of impurities of the silicon, the currentdensity, the type of electrolytic solution, and the like). In thiscontext, the relevant characteristic of the porous silicon is itsporosity (P_(PS)%), which is defined with respect to the (compact)silicon as:

where ρ_(PS) is the density of the porous silicon and ρ_(Si) is thedensity of the compact silicon (i.e., approximately 2.3 g/cm³). Thedensity of the porous silicon ρ_(PS) can be measured by applying thefollowing formula:

$\rho_{PS} = {\rho_{Si} - \frac{P_{Si} - P_{e}}{S \cdot d_{PS}}}$

where the values P_(Si) (initial weight of the wafer before the anodicprocess), P_(e) (ending weight of the wafer after the anodic process)and d_(PS) (thickness of the porous silicon region) can be measured,while the value S (extent of the exposed surface of the wafer beingsubject to the anodic process) is known. Particularly, the porosityincreases with the doping concentration of N-type, and it decreases withthe doping concentration of P-type. Moreover, the porosity increases asthe current density increases (above a minimum value), and/or as theelectrolytic solution concentration decreases.

The porosity of the porous silicon region is selected as a trade-offbetween the opposed requirements of good adhesion (high porosity) andgood mechanical stability (low porosity). For example, in an embodimentthe porosity of the porous silicon region is in the approximate rangeP_(PS)%=20%-80%, and for example P_(PS)%=approximately 30%-70%, such asP_(PS)%=approximately 50%. In any case, the porous silicon region shouldbe maintained relatively thin; for example, in an embodiment the poroussilicon region has a thickness lower than approximately 1 μm, and forexample lower than approximately 0.5 μm, such as approximately 0.2 μm.Indeed, in this way the metal of the contact terminal being formedthereon penetrates inside the pores of the whole porous silicon region,thereby consolidating its structure so as to avoid any mechanicalstability problem and to warrant a stable contact resistance.

For example, in each contact area there is formed a single poroussilicon region that extends on its whole surface (with a uniformporosity throughout it); this provides the best adhesion of thecorresponding contact terminal in a very simple way.

Alternatively, multiple porous silicon regions may be formed in eachcontact area. The porous silicon regions (with any shape—for example,rectangular, squared or circular) are distributed uniformly throughoutthe contact area. The concentration of the porous silicon regions in thecontact area determines its (average) force of adhesion as a whole. Forexample, a single porous region with a size of approximately 10 mm²(being made of a porous silicon that provides an adhesion ofapproximately 20 MPa) generates a force of adhesion of approximately(20·10⁶)·(10·10⁻⁶)=200N; the same result is achieved with 5 porousregions with a size of approximately 1 mm² being made of a poroussilicon that provides an adhesion of approximately 40 Mpa, which againgenerate a force of adhesion of approximately (40·10⁶)·(5.1·10⁻⁶)=200N.In this way, it is possible to alternate the effect of the poroussilicon regions (increasing the adhesion but reducing the mechanicalstability) with the one of the compact silicon (maintaining themechanical stability).

In another embodiment, the adhesion of the porous silicon regionsdecreases (on the contact area) by moving inwards from a border thereof.For example, the adhesion decreases from a maximum value (at the borderof the contact area) to a minimum value (at the center of the contactarea) equal to approximately 10%-50%, and for example equal toapproximately 20%-40%, such as equal to approximately 25%-35% of themaximum value. For example, the adhesion at the border of the contactarea may be about 150-250 MPa, while the adhesion at the center of thecontact area may be approximately 60-90 MPa. The desired result isachieved by reducing the concentration (i.e., the number and/or thesize) of the porous silicon regions while moving from the border to thecenter of the contact area. In this way, it is possible to have a highadhesion where the risk of detachment of the contact terminal is thehighest (i.e., at its border), and at the same time to guarantee a highmechanical stability (by reducing the porous silicon where the risk ofdetachment of the contact terminal is the lowest—i.e., at its center).

As a further improvement, the porosity of the porous silicon region ismodulated by decreasing it moving away from the corresponding contactarea. In this way, it is possible to have a higher porosity on thecontact area (so as to increase the adhesion of the correspondingcontact terminal) and a lower porosity inside the wafer (so as toguarantee its mechanical stability). Particularly, the porosity on thecontact area may also be set to very high values that would make thewafer mechanically unstable; indeed, the metal of the contact terminalbeing formed thereon that penetrates inside the pores of the poroussilicon region consolidates its structure (at the same time of anchoringthe contact terminal to the wafer). In this way, it is possible toobtain a very high adhesion with a good mechanical stability warrantinga stable contact resistance. For example, the porosity decreases fromP_(PS)%=approximately 70%-90% (such as P_(PS)%=approximately 75%-85%,like P_(PS)%=approximately 80%) at the contact area toP_(PS)%=approximately 10%-30% (such as P_(PS)%=approximately 15%-25%,like P_(PS)%=approximately 20%) at its maximum depth. Such result may beobtained by varying the process parameters accordingly (for example, bydecreasing the current density over time with a linear law).

Particularly, an electron microscopy photo of an exemplary poroussilicon region 125 that was made on the front surface of the wafer isshown in FIG. 3A (similar considerations apply to the porous siliconlayer on the back surface of the wafer). The porous silicon region 125(wherein higher porosity zones at the top are lighter and lower porosityzones at the bottom are darker) was obtained with a concentration of theelectrolytic solution equal to approximately 9% in volume of HF, byvarying the current density from approximately 150 mA/cm² toapproximately 15 mA/cm² in approximately 6 s; the porous silicon region125 has a porosity varying from P_(PS)%=approximately 80% toP_(PS)%=approximately 30%. This porous silicon region 125 provided anadhesion higher than approximately 210 MPa of the front contact terminalmade of approximately 0.25 μm of Nickel and approximately 20 μm ofCopper. As another example, a further porous silicon region was obtainedwith a concentration of the electrolytic solution equal to approximately25% in volume of HF, by varying the current density from approximately120 mA/cm² to approximately 10 mA/cm² in approximately 6 s; the obtainedporous silicon region has a porosity varying from P_(PS)%=approximately80% to P_(PS)%=approximately 50%. This porous silicon (being used on theback surface of the wafer) provided an adhesion higher thanapproximately 40-50 MPa of the back contact terminal made ofapproximately 0.4 μm of Nickel and approximately 15 μm of Copper. Inboth cases, the (front and back) contact terminals withstood thestandard tape test; moreover, the contact terminals did not lift offafter heating the wafer up to approximately 600° C., or even aftersubjecting it to a thermal shock from approximately −70° C. to 200° C.

Optionally, as shown in the schematic cross-section view of FIG. 3B, theporous silicon region 125 on the front surface of the wafer 105 (similarconsiderations apply to the porous silicon layer on the back surface ofthe wafer 105) may include, in addition to an external layer 325 e withmodulated porosity as above, an internal layer 325 i with uniformporosity. The internal layer 325 i has a porosity that is may be betweenthe maximum porosity and the minimum porosity of the external layer 325e (for example, P_(PS)%=approximately 20-40%, and for exampleP_(PS)%=approximately 25-35%, such as P_(PS)%=approximately 20% for anexternal layer with a porosity in the range from P_(PS)%=approximately80% to P_(PS)%=approximately 20%). For example, this result may beachieved with an anodization process at constant process parameters (forforming the internal layer 325 i) immediately after the anodizationprocess with variable process parameters as above (for forming theexternal layer 325 e). For example, the internal layer 325 i is thickerthan the external layer 325 e (e.g., with a thickness equal toapproximately 1-6 times, and for example equal to approximately 1.5-2.5times the one of the external layer 325 e); for example, in a poroussilicon region 125 with a thickness of approximately 0.75 μm, theexternal layer 325 e may be of approximately 0.25 μm and the internallayer 325 i may be of approximately 0.5 μm. The internal layer 325 iemphasizes the gettering effect of the porous silicon region 125.

With reference now to FIG. 4A-FIG. 4B together, there is shown asimplified cross-section view and a simplified bottom view,respectively, of a processing head 400 that can be used to process thesolar cell according to an embodiment.

Particularly, the processing head 400 is formed in a silicon substrate405. A delivery duct 410 crosses the silicon substrate 405 from an uppersurface thereof to a lower surface thereof; the delivery duct 410 endswith a corresponding delivery mouth 412 on the lower surface of thesubstrate 405. A delivery pump 415 is coupled to the delivery duct 410on the upper surface of the silicon substrate 405. A suction duct 420likewise crosses the silicon substrate 405 from its upper surface to itslower surface. The suction duct 420 ends with a corresponding suctionmouth 422 on the lower surface of the substrate 405; the suction mouth422 has a frame-like shape (for example, with a width of approximately10-200 μm), which is arranged around the delivery mouth 412 so as tototally surround it (for example, at a distance of approximately 1-250μm). A suction pump 425 (of the vacuum type with a regulation valve) iscoupled to the suction duct 420 on the upper surface of the siliconsubstrate 405 (for example, through a lung system).

In operation, the delivery pump 415 pumps a generic chemical solutioninto the delivery duct 410. The chemical solution is then delivered bythe delivery mouth 412 on the lower surface of the silicon substrate405. At the same time, the suction pump 425 creates a depression in thesuction duct 420. The depression at the suction month 422 around thedelivery mouth 412 immediately sucks back the chemical solution beingdelivered by the delivery mouth 412 (without being loosen by theprocessing head 400), as shown by the arrows in the figure. As a result,a dynamic drop 430 is formed on the lower surface of the siliconsubstrate 405 by the chemical solution (in correspondence to thedelivery mouth 412 and the suction mouth 422)—which dynamic drop 430will be transformed into a dynamic meniscus when in contact with anunderlying surface. Particularly, this dynamic drop 430 is formed by aportion of the chemical solution that remains attached under the siliconsubstrate 405; the dynamic drop 430 is in a fixed position, but itscontent is continuously refreshed (thanks to the flow of the chemicalsolution from the delivery duct 410 to the suction duct 420). The sizeof the dynamic drop 430 may be controlled dynamically (by correspondingcontrol means, not shown in the figure) by changing the inflow of thechemical solution that is delivered by the delivery duct 410 (throughthe delivery pump 415) and/or the depression at the suction duct 420(through the suction pump 425), and/or it may be controlled staticallyby setting the distance and the sizes of the suction mouth 422 and thedelivery mouth 412.

Moving to FIG. 5A-5B, there are shown the main stages of a process forproducing this processing head according to an embodiment.

As shown in FIG. 5A, the production process starts with two siliconwafers 505 u and 505 d with either the same or different type ofconductivity of the N-type or of the P-type (for example, with aresistivity of approximately 0.001-200 Ω·cm). One or more smallthrough-holes 510 u are made across the (upper) wafer 505 u (between anupper surface and a lower surface thereof); for example, thethrough-holes 510 u are made by a Deep Reactive Ion Etching (DRIE)process, which allows obtaining through-holes 510 u of circular sectionwith a diameter down to approximately 10 μm and a depth up toapproximately 750 μm. At the same time, a trench 520 ad is madeextending into the (lower) wafer 505 d from an upper surface thereof(for example, by a wet etching or plasma etching process).

Moving to FIG. 5B, the wafers 505 u and 505 d are superimposed (with thelower surface of the wafer 505 u in contact with the upper surface ofthe wafer 505 d) and aligned to each other; the wafers 505 u and 505 dare then bonded together (for example, by a silicon fusion bondingprocess). At this point, a through-hole 510 d is made across the wafer505 d (between a lower surface thereof and its upper surface); in planview, the through-hole 510 d embeds all the through-holes 510 u (insidethe trench 520 ad), so as to reach them. Moreover, a trench 520 bd ismade extending into the wafer 505 d from its lower surface (for example,by the DRIE process); the trench 520 bd extends in plan view along aframe that surrounds the through-hole 510 d, so as to reach the trench520 ad in proximity of its inner edge; likewise, a trench 520 u is madeextending into the wafer 505 u from its upper surface (for example, bythe DRIE process), so as to reach the trench 520 ad in proximity of itsouter edge. In this way, the through-holes 510 u and the through-hole510 d define the delivery duct of the processing head, while thetrenches 520 u, 520 ad and 520 bd define its suction duct. Theprocessing head is then completed by connecting the delivery pump andthe suction pump (not shown in the figure) to the through-holes 510 uand to the trench 520 u, respectively, on the upper surface of the wafer505 u; for this purpose, corresponding piping connections are sealed tothe wafer 505 u (for example, by a soldering or eutectic process—such asbased on gold-silicon).

The above-described structure may be produced in a very simple way.Indeed, in this case the different components of the processing head maybe formed by crossing separate wafers (with a reduced thickness); at thesame time, the wafers may be bonded together without too stringentaccuracy requirements.

The above-described processing head may also be made in polymericmaterial (such as Polyvinylidene fluoride, or PVDF). For example, thisresult may be achieved by using the above-described technology to make asilicon sacrificial insert with a negative structure with respect to theone of the FIG. 5B. More specifically, when the two silicon wafers arestill separated, small through-holes are made across the upper waferamong the areas where the through-holes 510 u are to be formed, and alarge through-hole (with a frame section) is made across the lower waferbetween the areas where the through-hole 510 d and the trench 520 bd areto be formed. After the two wafers have been bonded, silicon is removedfrom the upper wafer between the areas where the through-holes 510 u andthe trench 520 u are to be formed, and around the area where the sametrench 520 u is to be formed; moreover, silicon is removed from thelower wafer around the area where the trench 520 bd is to be formed,down to reach the area where the trench 520 ad is to be formed. Thesacrificial insert so obtained is now placed into a stamp for injectionmolding, which is brought to a temperature higher than a meltingtemperature of the polymeric material to be injected (such asapproximately 175-200° C. for the PVDF). At this point, the polymericmaterial is injected under pressure into the stamp, so as to fill allthe openings of the sacrificial insert (corresponding to the desiredprocessing head). The stamp is cooled down to room temperature, and thestructure so obtained is extracted. The sacrificial insert is thenremoved (by means of an etching process selective to the polymericmaterial). The processing head is completed by connecting the deliverypump and the suction pump (either during the stamping phase orafterwards). The proposed processing head may be advantageously used tosimplify several steps of the production process of the above-describedsolar cell, since its dynamic meniscus allows processing the waferselectively in specific areas thereof (on its front surface and/or backsurface). In this respect, it should be noted that this is the firsttime that a dynamic meniscus is proposed for use in the production ofsolar cells. Indeed, for example, U.S. Pat. No. 7,078,344 (the entiredisclosure of which is herein incorporated by reference) only describesthe use of a dynamic meniscus for implementing a selective etchingprocess to correct non-uniformity in overburden conductive material(which is formed in dual damascene manufacturing processes); in anycase, a corresponding proximity head that is described in this documentis formed by multiple distinct inlets and outlets that are spaced apartto each other, along parallel lines or concentric rings. Particularly,FIG. 6A-6B shows an exemplary etching module 600 according to anembodiment (which may be used to clear a portion of the contact area 122for the front contact terminal of the solar cell). Starting from FIG.6A, for this purpose the etching module 600 includes an etching(processing) head (denoted with the reference 601), which is suppliedwith an etching solution (for example, made of HF). The wafer 105 ismounted on a transport system 650 (for example, based on a belt), whichtransports the wafer 105 under the etching module 600.

As soon as the front surface of the wafer 105 is brought in contact witha dynamic drop of the etching head 601 (for example, by raising thewafer 105 towards the etching head 601), the dynamic drop becomes adynamic meniscus 630; the dynamic meniscus 630 then etch theanti-reflection coating 215 and the oxide layer 205. For example, adynamic meniscus 630 made of a concentrated solution of HF atapproximately 48% in volume completely removes the anti-reflectioncoating 215 and the oxide layer 205 in less than approximately 60 s(with this time that may be further reduced, for example, by increasingthe temperature of the etching solution and/or changing the etchingsolution). In this way, the contact area 122 may be cleared without theneed of any photolithography operation.

As a further improvement, as shown in FIG. 6B, in the meanwhile the belt650 shifts the wafer 105 under the etching module 600 (along acorresponding transport direction—for example, from the left to theright in the figure). In this way, the etching head 601 clears thecontact area 122 while crossing a corresponding portion of the wafer 105(moving under it). As a result, the contact area 122 may be formed as astrip that crosses the whole wafer 105 (along its transport direction)by means of a smaller etching head 601, with the same size of thecontact area 122 only transversally to the transport direction.Moreover, this allows processing a batch of wafers 105 continuallywithout stopping them (under the etching head 601).

With reference now to FIG. 7A-7B, there is shown an exemplaryanodization module 700 according to an embodiment (which may be used tomake a portion of the porous silicon region 125 for the front contactterminal of the solar cell). Starting from FIG. 7A, for this purpose theanodization module 700 includes three processing heads (denoted with thereferences 701 a, 701 b and 701 c). The anodization (processing) head701 b is supplied with an electrolytic solution (for example, being richof HF); at the same time, the anodization head 701 b is coupled to aterminal 703 b that provides a biasing voltage V− to its substrate. Thebiasing (processing) heads 701 a, 701 c are instead supplied with aconductive solution that does not etch the wafer 105 (for example, madeof KCl); at the same time, the biasing heads 701 a and 701 c are coupledto a common terminal 703 ac that provides a biasing voltage V+ (higherthan the biasing voltage V−) to both their substrates. The wafer 105 ismounted on a transport system 750 (for example, based on a belt), whichtransports the wafer 105 under the anodization module 700 (along acorresponding transport direction—for example, from the left to theright in the figure). The processing heads 701 a, 701 b, and 701 c arearranged in succession along this transport direction.

As soon as the front surface of the wafer 105 is brought in contact witha dynamic drop 730 a, 730 b, and 730 c of each processing head 701 a,701 b, and 701 c, respectively, the dynamic drop 730 a-730 c becomes acorresponding dynamic meniscus (denoted with the same reference)—inreality, the wafer 105 is far thinner than it is in the figure, so thatthe dynamic drops 730 a-730 c touch the belt 750 when outside the wafer105.

Particularly, when the contact area 122 reaches the biasing head 701 aand the anodization head 701 b (thereby forming the correspondingdynamic menisci 730 a and 730 b, respectively), an electrolytic cell isdefined by the biasing head 701 a and the anodization head 701 b—with acorresponding current flowing through the biasing head 701 a, thedynamic meniscus 730 a, the N-type layer 115, the dynamic meniscus 730b, and the anodization head 701 b; the N-type layer 115 in contact withthe dynamic meniscus 730 b (providing the electrolytic solution) is thenanodized, so as to form a corresponding portion of the porous siliconregion 125.

Continuing to FIG. 7B, when the contact area 122 reaches the biasinghead 701 c (thereby forming the corresponding dynamic meniscus 730 c),the biasing head 701 c adds as an anode to the above-describedelectrolytic cell—with a corresponding current flowing through thebiasing head 701 c, the dynamic meniscus 730 c, the porous siliconregion 125 already formed, the N-type layer 115, the dynamic meniscus730 b, and the anodization head 701 b. When the contact area 122 leavesthe biasing head 701 a, the electrolytic cell then remains formed by thebiasing head 701 c and the anodization head 701 b. As above, the N-typelayer 115 in contact with the dynamic meniscus 730 b is anodized tocontinue forming the porous silicon region 125, until its completionwhen the contact area 122 leaves the anodization head 701 b.

In this way, the porous silicon region 125 can be made in a very simpleway (without the need of contacting the wafer 105 on its back surface);this also improves the uniformity of the porous silicon region 125,since it avoids any electrical contact through the PN junction of thewafer 105. Moreover, the porous silicon region 125 may be formed as astrip that crosses the whole wafer 105 (along its movement direction) bymeans of smaller processing heads 701 a-701 c, with the possibility ofprocessing a batch of wafers continually without stopping them (underthe processing heads 701 a-701 c).

Considering FIG. 7C, there is shown an exemplary anodization module 700′according to another embodiment. In this case, the anodization module700′ only includes the anodization head 701 b (without any biasinghead); on the contrary, a terminal 703′ provides the same biasingvoltage V+ directly to the wafer 105, by contacting the thin metal layer220 on its back surface.

This implementation simplifies the structure of the anodization module700′, since it includes a single anodization head 701 b (at the cost ofa more complex structure for contacting the back surface of the wafer105).

Moving to FIG. 8A-8B, there is shown an exemplary deposition module 800according to an embodiment (which may be used to make a portion of thefront contact terminal of the solar cell with an electrolytic depositionprocess). Starting from FIG. 8A, for this purpose the deposition module800 includes three processing heads (denoted with the references 801 a,801 b and 801 c). The deposition (processing) head 801 b is suppliedwith an electrolytic solution including a salt of the metal to bedeposited (for example, Au, Ag, Pt, Ni, Cu, Co, Mo, Ru, PdCo, Pd, PdNi);at the same time, the deposition head 801 b is connected to a terminal803 b that provides a biasing voltage V+′ to its substrate. The biasing(processing) heads 801 a,801 c are instead supplied with a conductivesolution that does not etch the wafer 105 (for example, made of KCl, ora solution with organic additives in order to decrease dissolution ofthe metal deposited, or liquid metal (e.g., Hg, Ga), or conductiveliquid ink (e.g., non ionic solution plus metal nanoparticles or carbonnanotubes), or non-ionic solution (e.g., deionized water) used in caseof alternating current biasing); at the same time, the biasing heads 801a and 801 c are connected to a common terminal 803 ac that provides abiasing voltage V−′ (lower than the biasing voltage V+′) to both theirsubstrates. The wafer 105 is mounted on a transport system 850 (forexample, based on a belt), which transports the wafer 105 under thedeposition module 800 (along a corresponding transport direction—forexample, from the left to the right in the figure). The processing heads801 a, 801 b and 801 c are arranged in succession along this transportdirection.

As soon as the front surface of the wafer 105 is brought in contact witha dynamic drop 830 a, 830 b and 830 c of each processing head 801 a, 801b and 801 c, respectively, the dynamic drop 830 a-830 c becomes acorresponding dynamic meniscus (denoted with the same reference)—asabove, with the wafer 105 that is far thinner than it is in the figure,so that the dynamic drops 830 a-830 c touch the belt 850 when outsidethe wafer 105.

Particularly, when the porous silicon region 125 reaches the biasinghead 801 a and the deposition head 801 b (thereby forming thecorresponding dynamic menisci 830 a and 830 b, respectively), anelectrolytic cell is defined by the deposition head 801 b and thesubstrate 105, with the circuit that is closed by the liquid contactobtained from the substrate 105 to the biasing head 801 a—with acorresponding current flowing through the deposition head 801 b, thedynamic meniscus 830 b, the porous silicon region 125, the dynamicmeniscus 830 a, and the biasing head 801 a; a metal layer is thendeposited on the porous silicon region 125 in contact with the dynamicmeniscus 830 b (providing the electrolytic solution, with the metalsalts that are continuously replenished), so as to form a correspondingportion of the front contact terminal Tf.

Continuing to FIG. 8B, when the porous silicon region 125 reaches thebiasing head 801 c (thereby forming the corresponding dynamic meniscus830 c), the biasing head 801 c adds an electric contact to theabove-described electrolytic cell—with a corresponding current flowingthrough the deposition head 801 b, the dynamic meniscus 830 b, theporous silicon region 125, the front contact terminal Tf already formed,the dynamic meniscus 830 c, and the biasing head 801 c. When the poroussilicon region 125 leaves the biasing head 801 a, the electrolytic cellthen remains formed by the deposition head 801 b and the biasing head801 c. As above, the metal layer is deposited on the porous siliconregion 125 in contact with the dynamic meniscus 830 b to continueforming the front contact terminal Tf, until its completion when theporous silicon region 125 leaves the deposition head 801 b.

In this way, the front contact terminal Tf is formed by a fullelectrolytic deposition process, without the need of previously makingany thin metal layer by an electro-less deposition process (since thenegative voltage being required to bias the wafer 105 is now applied toits front surface). This allows making the front contact terminal Tfvery thick in a relatively short time (with a consequent reduction ofthe production cost of the solar cell); for example, the front contactterminal Tf may be made of Ni with a deposition rate up to approximately20 nm×minute or of Cu with a deposition rate of approximately 5-15μm×minute. Moreover, as above the front contact terminal Tf may beformed as a strip that crosses the whole wafer 105 (along its movementdirection) by means of smaller processing heads 801 a-801 c, with thepossibility of processing a batch of wafers continually without stoppingthem (under the processing heads 801 a-801 c).

Considering FIG. 8C, there is shown an exemplary deposition module 800′according to another embodiment. The deposition module 800′ is used toprocess a solar cell as above, which is now formed in a wafer 105′ ofthe N-type (i.e., with an upper P-type layer 115′ and a lower N-typelayer 120′). In this case, the deposition module 800′ only includes thedeposition head 801 b (without any biasing head); on the contrary, aterminal 803′ provides the same biasing voltage V−′ directly to thewafer 105′, by contacting the thin metal layer 220 on its back surface.This is now possible because the voltage that is applied between thedeposition head 801 b (V+′) and the back surface of the wafer 105′ (V−′)forward biases the PN junction 115′-120′, so that is does not interferewith the deposition process.

As above, this implementation simplifies the structure of the depositionmodule 800′, since it includes a single deposition head 801 b.

As a further improvement, in both cases (see FIG. 8A-FIG. 8B and FIG.8C) in the meanwhile the belt 850 may also move the wafer 105,105′ awayfrom the deposition head 801 b along a direction of deposition of themetal layer of the front contact terminal Tf—i.e., vertically (forexample, by lowering the wafer 150,105′). In this way, it is possible toform the front contact terminal Tf with an elongated shape, whichextends perpendicularly (i.e., upwards) from the front surface of thewafer 105,105′. In addition, the transport system 850 may also shift thewafer 105,105′ transversally to the deposition direction (for example,by rotating it); in this way, it is possible to obtain any complex shapeof the front contact terminal Tf (for example, spiral-like).

The above-mentioned additional features allow forming the front contactterminal Tf with a shape and a structure (either rigid or elastic) thatfacilitates its coupling; moreover, this result is achieved in a verysimple way.

Considering now FIG. 9A, there is shown a schematic block diagram of aproduction line 900 of the solar cells according to an embodiment.

Particularly, the production line 900 includes a pipeline of an etchingstation 905, an anodization station 910 and a deposition station 915; afeeding system 950 (for example, based on a belt) feeds a batch ofwafers 105,105′ in succession across the etching station 905, theanodization station 910 and the deposition station 915 (along acorresponding feeding direction, from the left to the right in thefigure). The etching station 905 is formed by one or more of theabove-described etching modules (arranged transversally to the feedingdirection—i.e., vertically in the figure), each one for clearing acorresponding portion of a contact area in the wafer 105,105′ currentlyunder it. The anodization station 910 is formed by one or more of theabove-described anodization modules (arranged transversally to thefeeding direction—i.e., vertically in the figure), each one for making acorresponding portion of a porous silicon region in a further wafer105,105′ currently under it. The deposition station 915 is formed by oneor more of the above-described deposition modules (arrangedtransversally to the feeding direction—i.e., vertically in the figure),each one for making a corresponding portion of a (front and/or back)contact terminal in a still further wafer 105,105′ currently under it.

In this way, the wafers 105,105′ may be processed continually, evenwithout stopping them under the different stations 905-915. This allowsobtaining a very high throughput of the production line 900, whichdramatically reduces the production cost of the solar cells; forexample, after a latency time (required by a first wafer 105,105′ topass trough the whole production line 900), the throughput of theproduction line 900 can reach approximately 3,000-4,000 solar cells perhour.

The etching station 905, the anodization station 910 and the platingstation 915 may have different architectures.

Particularly, in an embodiment of the invention (as shown in FIG. 9B),the etching station 905 includes, for each contact strip of the frontcontact terminal (seven in the example at issue), the etching module 600as above—with its etching head, in the present example, which is shorterthan the wafer 105 along its feeding direction (from the left to theright). The anodization station 910 includes, for each contact strip ofthe front contact terminal, the anodization module 700 as above—with itsthree processing heads (i.e., one anodization head and two biasingheads) that are again shorter than the wafer 105 along its feedingdirection. Likewise, the plating station 915 includes, for each contactstrip of the front contact terminal, the plating module 800 asabove—with its three processing heads (i.e., one plating head and twobiasing heads) that are again shorter than the wafer 105 along itsfeeding direction.

Moving to FIG. 9C, when the wafer 105 passes through the etching station905, each etching module 600 clears a corresponding strip of the contactarea 122 in the wafer 105 (with the strip of the contact area 122 thatcrosses the whole wafer 105 along its feeding direction).

With reference now to FIG. 9D, when the wafer 105 passes through theanodization station 910, each anodization module 700 forms acorresponding strip of the porous silicon region 125 in the associatedcontact area (with the strip of the porous silicon region 125 thatcrosses the whole wafer 105 along its feeding direction).

At the end, as shown in FIG. 9E, when the wafer 105 passes through theplating station 915, each plating module 800 forms the correspondingcontact strip of the front contact terminal Tf on the associated poroussilicon region (with the contact strip that crosses the whole wafer 105along its feeding direction).

The above-described structure allows forming the front contact terminalTf without any protective photo-resist mask on the anti-reflectioncoating of the wafer, since the anodization modules 700 applies theelectrolytic solution only where it is necessary (i.e., on thecorresponding strips of the porous silicon region); moreover, in thiscase it is possible to use whatever electrolytic solution without anyrisk of damaging the anti-reflection coating.

In a different embodiment (as shown in FIG. 9F), the etching station 905is the same as above. Instead, the anodization station 910 includes asingle anodization module 700 for all the contact strips of the frontcontact terminal—with its three processing heads that extends along thewhole width of the wafer 105 transversally to its feeding direction(i.e., vertically in the figure). Likewise, the plating station 915includes a single plating module 800 for all the contact strips of thefront contact terminal—with its three processing heads that extendsalong the whole width of the wafer 105 transversally to its feedingdirection.

Moving to FIG. 9G, as above when the wafer 105 passes through theetching station 905, each etching module 600 clears the correspondingstrip of the contact area 122 in the wafer 105 (with the strip of thecontact area 122 that crosses the whole wafer 105 along its feedingdirection).

With reference now to FIG. 9H, when the wafer 105 passes through theanodization station 910, the anodization module 700 forms all the stripsof the porous silicon region 125 in the contact area (with the strips ofthe porous silicon region 125 that cross the whole wafer 105 along itsfeeding direction); in this respect, it is noted that, even though theanodization module 700 acts on the whole wafer 105, it is effective onlyon the contact area that is not covered by the protective layer of thewafer 105.

At the end, as shown in FIG. 9I, when the wafer 105 passes through theplating station 915, the plating module 800 forms all the contact stripsof the front contact terminal Tf on the porous silicon region (with thecontact strips that cross the whole wafer 105 along its feedingdirection). As above, even though the plating module 800 acts on thewhole wafer 105, it is effective only on the porous silicon region thatis not covered by the protective layer of the wafer 105.

The above-described structure simplifies the production line (but itentails the use of an electrolytic solution that does not damage theantireflection coating of the wafer 105—for example, with aconcentration of HF lower than approximately 20%).

In both cases, it is possible to use a similar structure to form the twocontact buses of the front contact terminal (after rotating the wafer byapproximately 90°—such as by means of a corresponding rotatingplatform)—for example, with a further etching station, anodizationstation and deposition station that are arranged downstream theabove-described etching station, anodization station and depositionstation, respectively.

In another embodiment (as shown in FIG. 9J), the etching station 905includes a single etching module 600 with the same shape of the wholefront contact terminal (including its contact strips and contact buses).Likewise, the anodization station 910 includes a single anodizationmodule 700′ with the same shape of the whole front contact terminal Theplating station 915 instead includes the same plating module 800 asabove, with its three processing heads that extends along the wholewidth of the wafer 105 transversally to its feeding direction (similarconsiderations apply if the plating station 915 includes three distinctprocessing heads for each contact strip of the front contact terminal).

Passing to FIG. 9K, the wafer 105 moves towards the etching station 905without entering in contact thereto (for example, because it is loweredor spaced apart laterally); when the wafer 105 reaches the desiredposition under the etching station 905, it is stopped and brought incontact thereto (for example, by moving it upwards or laterally). Inthis way, the etching module 600 in one-shot clears the whole contactarea 122 (for the front contact terminal) in the wafer 105.

With reference now to FIG. 9L, the wafer 105 is moved away from theetching station 905 (for example, downwards or laterally), and thenmoved towards the anodization station 910; when the wafer 105 reachesthe desired position under the anodization station 910, it is stoppedand brought in contact thereto (for example, by moving it upwards orlaterally). In this way, the anodization module 700′ in one-shot formsthe whole porous silicon region 125 in the contact area.

At the end, as shown in FIG. 9M, the wafer 105 passes through theplating station 915, wherein the plating module 800 forms the wholefront contact terminal Tf on the porous silicon region as above.

The above-described structure allows forming the porous silicon regionwith whatever shape in a single passage, without any constraint on theelectrolytic solution (but it does not allow processing the wafers 105continually without stopping them).

In a further embodiment (as shown in FIG. 9N), the production line isused to process wafers 105′ of the N-type. In this case, the etchingstation 905 includes a single etching module 600 with the same shape ofthe whole front contact terminal as above. Likewise, the depositionstation 915 includes a single deposition module 800′ with the same shapeof the whole front contact terminal. The anodization station 910 insteadincludes the same anodization module 700 as above, with its threeprocessing heads that extends along the whole width of the wafer 105′transversally to its feeding direction (similar considerations apply ifthe anodization station includes three distinct processing heads foreach contact strip of the front contact terminal).

Passing to FIG. 9O, the wafer 105′ again moves towards the etchingstation 905 without entering in contact thereto; when the wafer 105′reaches the desired position under the etching station 905, it isstopped and brought in contact thereto, so that the etching module 600in one-shot clears the whole contact area 122 in the wafer 105′.

With reference now to FIG. 9P, as above the wafer 105′ passes throughthe anodization station 910, wherein the anodization module 700 formsthe whole porous silicon region 125 in the contact area.

At the end, as shown in FIG. 9M, the wafer 105′ moves towards thedeposition station 915 without entering in contact thereto (for example,because it is lowered or spaced apart laterally); when the wafer 105′reaches the desired position under the deposition station 915, it isstopped and brought in contact thereto (for example, by moving itupwards or laterally). In this way, the deposition module 800′ inone-shot forms the whole front contact terminal Tf on the porous siliconregion.

The above-described structure allows forming the front contact terminalTf with whatever shape in a single passage, without any constraint onthe electrolytic solution (but it does not allow processing the wafers105′ continually without stopping them).

Additional structures of the production line may be obtained bycombining the above-described etching station, anodization station, anddeposition station in different ways. For example, in a furtherembodiment the etching station 905 and the anodization station 910 ofthe FIG. 9B are used to form the portions of the contact area and of theporous silicon region, respectively, for the contact strips when thewafer 105 passes through them. A further etching station and a furtheranodization station with the same structure are then used to form theportions of the contact area and of the porous silicon region,respectively, for the contact buses when the wafer 105 (after beingrotated by approximately 90°) passes through them. The depositionstation 915 of the FIG. 9F is then used to form the contact strips andthe contact buses at the same time when the wafer 105 (after beingrotated by any angle higher than 0° and lower than 90°, for example,between 40° and 50°, such as 45°) passes through it. Alternatively, thesame result may also be obtained by using the anodization station 910 ofthe FIG. 9F to form the whole porous silicon region at the same timewhen the wafer 105 (after being rotated by 45°) passes through it.

In this way, the wafers 105 may be processed continually withoutstopping them under the different stations 905-915 with a reduced numberthereof. Naturally, in order to satisfy local and specific requirements,a person skilled in the art may apply to the embodiments described abovemany logical and/or physical modifications and alterations. Morespecifically, although this disclosure includes a certain degree ofparticularity with reference to one or more embodiments thereof, itshould be understood that various omissions, substitutions and changesin the form and details as well as other embodiments are possible.Particularly, different embodiments may even be practiced without thespecific details (such as the numerical examples) set forth in thepreceding description to provide a more thorough understanding thereof;conversely, well-known features may have been omitted or simplified inorder not to obscure the description with unnecessary particulars.Moreover, it is expressly intended that specific elements and/or methodsteps described in connection with any embodiment may be incorporated inany other embodiment as a matter of general design choice.

For example, similar considerations apply if the solar cell has adifferent structure or includes equivalent components (either separateto each other or combined together, in whole or in part); moreover, thesolar cell may have different operative characteristics. For example,the solar cell may be of the mono-layer type, of the multi junctiontype, and the like.

More generally, the same solution may also be applied to anyphotovoltaic cell (adapted to convert whatever kind of light energy intoelectric energy). Likewise, the solar cell may be made in a substrate ofa different starting silicon material (e.g. N-type mono-crystalline orpoly-crystalline) and/or different semiconductor material that allowsforming a corresponding layer of porous semiconductor material (such asGe, GaP, InP, SiC, and Si_(1-x)Ge_(x)). The contact terminals may bemade of one or more different conductive materials (for example, withthe addition of a solder-wettable layer); moreover, the contactterminals may have any shape or profile (for example, with the backcontact terminal having a grid structure as well), and they may bearranged in any number in whatever position (even all of them on thesame front or back surface of the substrate—for example, only with backcontacts but no front contact).

Likewise, the porous semiconductor regions of each contact area may haveany shape and they may be arranged in any number in whatever position.For example, it is possible to provide a single porous semiconductorregion only in part of the contact area (for example, a strip or a framearound its border).

Each porous semiconductor region may have different values of porosity;moreover, the porosity may decrease moving away from the correspondingsurface of the substrate in another way (for example, within a differentrange).

Each porous semiconductor region may have different thickness (with thecorresponding contact terminal that may also not penetrate completelywithin its whole thickness).

The additional layer of (uniform) porous semiconductor (acting asgettering center) may have any other thickness and/or porosity (even ifthis feature is merely optional).

Likewise, the porous silicon region may have a different porosity on thecontact area (even changing continually inwards from its border).

Similar considerations apply if the processing head has a differentstructure or includes equivalent components (either separate to eachother or combined together, in whole or in part). For example, eachdelivery and/or suction mouth may have any shape and size (for example,with circular, squared, cross-like, or of whatever complex patternprofile). Likewise, the suction duct may be arranged at a differentdistance from the delivery duct (even changing according to the width ofthe adjacent portion of the delivery duct). In any case, the processinghead may be used either to process the solar cell on its front surfaceand/or on its back surface. Moreover, the same structure may be obtainedwith equivalent processes (for example, by directly making through-holesthat cross the whole substrate with any kind of mechanical and laserdrilling processes). In any case, the proposed processing head lendsitself to be used turned top-down (so as to act on the substrate placedabove it).

The processing heads may also be made of any other (conductive and/orinsulating) material—for example, by inserting metal contacts to allowapplying the required biasing voltages between the processing head andthe wafer (either for the anodization process or for the depositionprocess); particularly, it is possible to form each processing head insilicon with a combination of different substrates of P-type and N-typethat (after being bonded to each other) form a processing head that maybe reverse or forward biased depending on the applied voltage.

In any case, the suction duct (of the anodization/deposition head) maybe arranged around the delivery duct in a different way—even withdistinct elements being placed close to each other (particularly forsimple shapes thereof, where it is not required that the delivery ductshould be completely surrounded by the suction duct). Different voltagesmay be used during either the anodization process or the depositionprocess (for example, with voltages varying around an average value in apulse deposition process, with voltages of reverse polarity during ashort period of the deposition process to increase the properties of thecontact terminals, and the like). More generally, theanodization/deposition head and the wafer may be biased to any voltagesthat allow creating a conductive path between them.

Nothing prevents controlling the size of the dynamic menisci in anyother way, or to have the dynamic menisci always with fixed size.Similar considerations apply if the wafer and the processing heads movewith respect to each other in a different way (for example, by movingthe processing heads in addition or in alternative to the wafer). In adifferent embodiment, the anodization/deposition module acting on asingle surface of the wafer may be formed by only two heads (i.e., theanodization/deposition head and a single biasing head). In this case, itis generally not possible to treat the whole contact area (since therequired conductive path between the two heads breaks as soon as one ofthem leaves the wafer); however, this may be not a problem in specificapplications (for example, when the anodization module is used to formthe porous semiconductor region that may also not extend throughout thewhole contact area).

The desired movement of the deposition head with respect to the wafer(for forming the contact terminals with elongated shape) may be achievedin any other way—for example, by moving the deposition head in additionor in alterative to the wafer; moreover, the movement may be of anyother type (for example, only perpendicular to the front/back surface ofthe wafer, only parallel thereto, or any combination thereof).

Likewise, the production line may have a different structure or it mayinclude equivalent components (either separate to each other or combinedtogether, in whole or in part). For example, nothing prevents providinga parallel structure wherein more solar cells are processed concurrently(so as to further increase the throughput of the production line).Moreover, the above-described architectures of the production line maybe combined to each other (with their different modules that may bearranged either in succession or interleaved). In any case, theproduction line may also be used to process the solar cells in adifferent way; for example, it is possible to implement part of theabove-described operations only, down to a single one (for example,without the etching station), to process the back surface of the wafersin a similar way, and the like.

Similar considerations apply if the contact terminal, the porous siliconregion and the contact area have different size and/or shape (forexample, with any other number of strips with whatever width andarrangement).

The substrate may be rotated with other equivalent means and/or by otherangles in whatever position along the production line.

An embodiment lends itself to be implemented with an equivalent method(by using similar steps, removing some steps being non-essential, oradding further optional steps); moreover, the steps may be performed ina different order, concurrently or in an interleaved way (at least inpart).

Particularly, the porous semiconductor may be formed with any othertechnique—such as by a spark erosion or a stain etching process (forexample, see “Pits and Pores II: Formation, properties, and significancefor advanced materials, ISBN 1566772923”, the entire disclosure of whichis herein incorporated by reference). Similar considerations apply tothe deposition process of the contact terminals, which may be completelyof the electro-less type, completely of the electrolytic type, or of anycombination thereof (or more generally with the contact terminals thatare made with any other additional and/or alternative process).

Moreover, the porosity may be modulated (within the wafer) in adifferent way—for example, by varying the current density betweendifferent values and/or with any other time pattern (for example,according to a linear, parabolic or logarithmic law); the same resultmay also be achieved by acting on any other parameter of the anodicprocess (or a combination thereof), such as the temperature, or byvarying the doping concentration of the substrate. In any case, the useof porous semiconductor regions with a uniform porosity within thesubstrate is contemplated.

Although in the preceding description reference has been made to solarcells, it should be understood that the same technique lends itself tobe applied in different applications. For example, the poroussemiconductor regions may be used to anchor thin metal layers on asubstrate for their bonding to other structures, especially in localizedeutectic bonding between silicon and gold for the encapsulation ofMicroElectroMechanical Systems (MEMSs), or more generally whenever ahigh adhesion of a thin or thick metal layer on a semiconductorsubstrate is required.

In any case, the above-described head, module and/or production line mayalso be used in other applications (whenever etching, anodization and/ordeposition processes are required). More generally, an embodiment of theproposed structure lends itself to implement a general-purposeelectrolytic cell. For example, in a different embodiment it is possibleto deposit any three-dimensional structure on a conductive substrate(for example, made of metal or silicon)—either with multiple heads (forbiasing the substrate on the same surface) or with a single head (withthe direct biasing of the substrate on its opposite surface). For thispurpose, each head and the substrate may move away from each otherduring the deposition (for example, by raising the head and/or loweringthe substrate) to form elongated structures with any height and shape(according to the geometry of the dynamic meniscus as defined by thecorresponding delivery and suction months). For example, rods (with anysection) may be obtained with the above-described heads; alternatively,tubes may be obtained by adding a further suction mouth inside thedelivery duct so as to create an empty region inside the dynamicmeniscus. In addition, it is also possible to obtain structures withvariable section along their length (for example, of the helicoidaltype) by also moving the head and/or the substrate transversally duringtheir spacing apart (for example, with a rotational component).Particularly, the structures so obtained may be used in probe cards,packaging substrates, electro-medical electrodes, MEMS structures, andthe like (with the possible addition of a polymeric or ceramic precursormaterial between them).

From the foregoing it will be appreciated that, although specificembodiments have been described herein for purposes of illustration,various modifications may be made without deviating from the spirit andscope of the disclosure. Furthermore, where an alternative is disclosedfor a particular embodiment, this alternative may also apply to otherembodiments even if not specifically stated.

1. An electrolytic module for performing an electrolytic process on asubstrate the electrolytic module including a set of processing headseach one including: a support element having an operative surface, atleast one delivery mouth for delivering a solution on the operativesurface, the support element being made at least partially of anelectrically conductive material for contacting the solution, at leastone suction mouth arranged around said at least one delivery month onthe operative surface for sucking the delivered solution thereby forminga dynamic meniscus on the operative surface when in contact with acorresponding portion of the substrate; one of the processing headsbeing an electrolytic head for providing a dynamic meniscus of anelectrolytic solution, wherein the electrolytic module further includes:first biasing means for applying a first biasing voltage to theelectrolytic solution through the electrolytic head, and second biasingmeans for applying a second biasing voltage to the substrate.
 2. Theelectrolytic module according to claim 1, wherein the support element ofeach processing head is made of a semiconductor material or of apolymeric material with a contact terminal for electrically contactingthe solution.
 3. The electrolytic module according to claim 1, whereinthe electrolytic head acts on a first surface of the substrate thesecond biasing means including means for applying the second biasingvoltage to a second surface of the substrate opposite the first surfaceof the substrate to create a conductive path with the electrolytic headthrough the substrate.
 4. The electrolytic module according to claim 1,wherein the electrolytic head acts on a first surface of the substratethe second biasing means including at least one biasing head of theprocessing heads each one for providing a dynamic meniscus of aconductive solution, and means for applying the second biasing voltageto the conductive solution through each biasing head, said at least onebiasing head acting on the first surface of the substrate to create aconductive path with the electrolytic head through the substrate.
 5. Theelectrolytic module according to claim 4, further including moving meansfor moving the substrate and the electrolytic module with respect toeach other along a movement direction, said at least one biasing headincluding a first biasing head and a second biasing head arrangedupstream and downstream, respectively, the electrolytic head along themovement direction for maintaining the conductive path while thesubstrate passes through the electrolytic module.
 6. The electrolyticmodule according to claim 1, further including means for controlling asize of the dynamic meniscus by changing an inflow of the solutionand/or a depression in each suction mouth.
 7. The electrolytic moduleaccording to claim 1, wherein the electrolytic module is an anodizationmodule for performing an anodization process on the substrate.
 8. Theelectrolytic module according to claim 7, wherein the anodization moduleincludes means for forming porous semiconductor regions on thesubstrate.
 9. The electrolytic module according to claim 1, wherein theelectrolytic module is a deposition module for electrolyticallydepositing conductive structures (Tf,Tb) on the substrate.
 10. Theelectrolytic module according to claim 9, wherein the deposition modulefurther includes means for moving away the substrate and theelectrolytic head along a deposition direction of the conductivestructures (Tf,Tb) transversally to the substrate during the depositionthereof to obtain an elongated shape of the conductive structures alongthe deposition direction.
 11. The electrolytic module according to claim10, wherein the deposition module further includes means for moving thesubstrate and the electrolytic head along a shifting directiontransversally to the deposition direction during the deposition of theconductive structures (Tf,Tb) to obtain a variable section of theconductive structures along the deposition direction.
 12. Theelectrolytic module according to claim 11, wherein the means for movingthe substrate and the electrolytic head (801 b) along the shiftingdirection includes means for rotating the substrate with respect to theelectrolytic head during the deposition of the conductive structures(Tf,Tb).
 13. The electrolytic module according to claim 9, wherein thedeposition module includes at least one further suction mouth arrangedinside each delivery month on the operative surface for sucking thedelivered solution thereby forming an empty region inside thecorresponding dynamic meniscus to generate a hollow structure of theconductive structures (Tf,Tb).
 14. An etching module for performing anetching process on a substrate the etching module including an etchinghead including: a support element having an operative surface, at leastone delivery mouth for delivering an etching solution on the operativesurface, and at least one suction mouth completely surrounding said atleast one delivery month on the operative surface for sucking thedelivered etching solution thereby forming a dynamic meniscus on theoperative surface when in contact with a corresponding portion of thesubstrate.
 15. The etching module according to claim 14, furtherincluding means for controlling a size of the dynamic meniscus bychanging an inflow of the solution and/or a depression in each suctionmouth.
 16. (canceled)
 17. The production line according to claim 16,further including means for feeding each substrate across the etchingstation, the anodization station and/or the deposition station along afeeding direction.
 18. The production line according to claim 17,wherein the etching station includes, for each one of a plurality ofstrips of the contact area, an etching module for forming thecorresponding strip of the contact area when the substrate passesthrough the etching station, and/or the anodization station includes,for each one of a plurality of strips of the porous semiconductor regionan anodization module for forming the corresponding strip of the poroussemiconductor region when the substrate passes through the anodizationstation, and/or the deposition station includes, for each one of aplurality of strips of the contact terminal (Tf,Tb), a deposition modulefor forming the corresponding strip of the contact terminal when thesubstrate passes through the deposition station.
 19. The production lineaccording to claim 17, wherein the anodization station includes a singleanodization module extending transversally to the feeding direction forforming a plurality of strips of the contact area when the substratepasses through the anodization station, and/or the deposition stationincludes a single deposition module extending transversally to thefeeding direction for forming a plurality of strips of the contactterminal when the substrate passes through the deposition station. 20.The production line according to claim 18, wherein each electrolytichead of the etching station, the anodization station and/or thedeposition station is shorter than the substrate along the feedingdirection.
 21. The production line according to claim 18, furtherincluding: means for first rotating the substrate exiting the etchingstation by a first rotation angle equal to 90°, and a further etchingstation for forming a set of further strips of the contact areaextending perpendicularly to said strips of the contact area when thefirst rotated substrate passes through the further etching station,and/or means for second rotating the substrate exiting the anodizationstation by a second rotation angle equal to 90°, and a furtheranodization station for forming a set of further strips of thesemiconductor porous region extending perpendicularly to said strips ofthe semiconductor porous region when the second rotated substrate passesthrough the further anodization station, and/or means for third rotatingthe substrate exiting the deposition station by a third rotation angleequal to 90°, and a further deposition station for forming a set offurther strips of the contact terminal (Tf) extending perpendicularly tosaid strips of the contact terminal when the third rotated substratepasses through the further deposition station.
 22. The production lineaccording to claim 18, further including: means for fourth rotating thesubstrate exiting the etching station by a fourth rotation angle higherthan 0° and lower than 90° to cause the anodization station to form thesemiconductor porous region when the fourth rotated substrate passesthrough the anodization station, and/or means for fifth rotating thesubstrate exiting the anodization station by a fifth rotation anglehigher than 0° and lower than 90° to cause the deposition station toform the contact terminal (Tf) when the fifth rotated substrate passesthrough the deposition station.
 23. The production line according toclaim 22, wherein said fourth rotating angle and said fifth rotatingangle are equal to 45°.
 24. The production line according to claim 17,wherein the etching station includes a single etching module for formingthe contact area when the substrate is stopped in the etching stationand coupled therewith, and/or the anodization station includes a singleanodization module for forming the semiconductor porous region when thesubstrate is stopped in the anodization station and coupled therewith,and/or the deposition station includes a single deposition module forforming the contact terminal (Tf) when the substrate is stopped in thedeposition station and coupled therewith.
 25. A photovoltaic cellincluding a substrate of semiconductor material, a plurality of contactterminals (Tf,Tb) each one arranged on a corresponding contact area ofthe substrate for collecting electric charges being generated in thesubstrate by the light, for at least one of the contact areas thesubstrate including at least one porous semiconductor region extendingfrom the contact area into the substrate for anchoring the wholecorresponding contact terminal on the substrate: wherein each poroussemiconductor region has a porosity decreasing moving away from thecontact area inwards the substrate.
 26. The photovoltaic cell accordingto claim 25, wherein each porous semiconductor region has a thicknesslower than 1 μm, the corresponding contact terminal (Tf,Tb) beingpenetrated inside the whole thickness of the region of poroussemiconductor region.
 27. The photovoltaic cell according to claim 25,wherein each porous semiconductor region includes an external layerproximate to the corresponding contact area with decreasing porosity andan internal layer distal from the contact area with uniform porosity.28. The photovoltaic cell according to claim 27, wherein the porosity ofthe external layer decreases from a maximum value to a minimum value,and wherein the porosity of the internal layer is comprised between saidmaximum value and said minimum value.
 29. The photovoltaic cellaccording to claim 27, wherein the internal layer is thicker than theexternal layer.
 30. The photovoltaic cell according to claim 25, whereinsaid at least one porous semiconductor region of each contact area has aporosity decreasing moving inwards the contact area from a borderthereof.
 31. The photovoltaic cell according to claim 30, wherein saidat least one porous semiconductor region each contact area includes aplurality of porous semiconductor regions decreasing in concentrationand/or size moving inwards the contact area from the border thereof. 32.A process for producing a photovoltaic cell, the process including thesteps of: providing a substrate of semiconductor material having a frontsurface for absorbing the light, forming at least one front contactterminal (Tf) arranged on a front contact area of the front surface forcollecting electric charges being generated in the substrate by thelight, wherein the front contact area and the front contact terminalhave a flat profile, the step of forming at least one front contactterminal including: forming at least one front porous semiconductorregion extending from the front contact area into the substrate foranchoring the whole front contact terminal on the substrate, andchemically depositing the front contact terminal.
 33. The processaccording to claim 32, wherein the step of forming at least one frontcontact terminal is performed at a temperature lower than 350° C. 34.The process according to claim 32, wherein the step of forming at leastone front porous semiconductor region includes: subjecting a front layerof the substrate corresponding to the porous semiconductor region to ananodic process in a dark condition, the front layer being silicon of theN-type with a doping concentration lower than 1·10¹⁷ atoms/cm³.
 35. Theprocess according to claim 34, the dark condition is lower then 2 lux.